Code Generation for Data Processing
Contents
Code generation is a key technique for efficient program execution and data processing. This lecture will cover the following topics from a practical perspective with accompanying hands-on exercises:
- Execution models of programs (interpretation, bytecode, machine code generation, etc.)
- Program representations (source code, intermediate representations (IRs), different forms of bytecode)
- Classical techniques of code generation
- SSA and optimization techniques, exemplary described on LLVM-IR
- Machine code generation: instruction selection and register allocation
- Execution of programs in virtual machines (e.g., WebAssembly, BPF, JavaScript)
- Sandboxing and optimizations for JIT compilation
- Execution of database queries (e.g., SQL, data frame API)
- Execution models and code representations
- Execution of machine code/binary translation (e.g., RISC-V)
- Specifics when translating machine code
Organization
- Lecture with integrated exercises: Thu 10–14 (c.t., with break) in 02.11.018
- Exercises will include hands-on programming tasks
- Language: English
- Module: CIT3230001, 6 ECTS, Bachelor/Master elective
- Area "Databases and Information Systems" for Informatics, Wirtschaftsinformatik/Information Systems, Informatics: Games Engineering, Biomedical Engineering
- B1.2 "Advanced Topics in Data Engineering" for Data Engineering and Analystics
- Written exam (90 minutes), might change to oral on low registration count
- Zulip stream for this lecture; private contact via e-mail
Prerequisites
The course is aimed at bachelor/master students who have taken the following (or similar) courses:
- IN0004 Introduction to Computer Architecture
- IN0008 Fundamentals of Databases
Material
Material and exercises will be regularly provided throughout the semester. All slides: [lec.pdf] [prs.pdf]
Exam: [exam.pdf] (will be provided after the exam)
| Date | Lecture Topic | Homework |
|---|---|---|
| 20.10. | Overview, Motivation, Interpretation Techniques [lec01.pdf]
Exercise: (no exercise session) | [hw01.txt] |
| 27.10. | Compiler Front-end [lec02.pdf]
Exercise: discussion of hw01 | [hw02.txt] [hw02-sol.cc] |
| 03.11. | IR Concepts, Control Flow Graph, SSA Construction [lec03.pdf] [prs03.pdf]
Exercise: in-class exercise on IR design [ex03.txt] | (none) |
| 10.11. | LLVM-IR and IR Design Considerations [lec04.pdf]
Exercise: discussion of hw02 | [hw04.txt] [hw04-sol.cc] |
| 17.11. | Analyses and Transformations [lec05.pdf] [prs05.pdf]
Exercise: writing an LLVM-IR pass [ex05.txt] | (none) |
| 24.11. | Instruction Selection [lec06.pdf] [prs06.pdf]
Exercise: discussion of hw04 | [hw06.txt] [hw06-sol.cc] |
| 01.12. | (no lecture/exercise, Dies Academicus) | |
| 08.12. | Register Allocation [lec07.pdf] [prs07.pdf]
Exercise: discussion of hw06 | [hw07.txt] [hw07-sol.cc] |
| 15.12. | Object Files, Linker, Loader [lec08.pdf]
Exercise: (none) | (none) |
| 22.12. | Unwinding and Debuginfo [lec09.pdf] [prs09.pdf]
Exercise: discussion of hw07 | [hw09.txt] |
| 12.01. | JIT-compilation and Sandboxing [lec10.pdf]
Exercise: WebAssembly hands-on [ex10.txt] | (none) |
| 19.01. | Binary Translation [lec11.pdf]
Exercise: discussion of hw09 and QEMU hands-on [ex11.txt] | [hw11.txt] |
| 26.01. | Query Compilation [lec12.pdf]
Exercise: SQLite hands-on [ex12.txt] | (none) |
| 02.02. | Vectorization [lec13.pdf]
Exercise: discussion of hw11 | (none) |
| 09.02. | Code Generation for GPUs (Nicolai Hähnle, AMD) [CodegenForGPUs.pdf] Wrap-up (second half of lecture) Exercise: (none) |